The invention relates to the field of manufacturing of MOS-type integrated circuits and more particularly to the manufacturing of integrated circuits comprising electrically programmable non-volatile memory transistors with floating gate (EPROM transistors) and logic transistors.
In such integrated circuits, the floating gates of the EPROM memory transistors are constituted by a first polysilicon level. A gale oxide layer separates those floating gates from the silicon substrate on which the transistors are formed.
Word lines, formed by a second polysilicon level, are arranged above the floating gates and correspond to the control gates of the memory transistors at the position of those transistors. An isolation layer, also called an interpoly oxide layer, is arranged between the word lines and the floating gates.
The logic transistors comprise a gate realized with the second polysilicon level used for forming the word lines of the memory. The gates of the logic transistors are separated from the substrate by a second gate oxide layer, different from the layer arranged under the floating gate of the memory transistors.
The sources and drains of the memory transistors are constituted by highly doped areas. The sources and drains of the logic transistors are formed by two regions. A first low doped region and a second highly doped region included in the first region.
An additional isolation layer is formed and contacts are established through etching of this additional isolation layer. A metal layer is deposited and etched for forming, especially in the memory area, bit lines crossing the word lines, while being isolated from the word lines, and contacting the drains of the memory transistors.
In a conventional manufacturing process, the following distinct steps are successively carried out:
forming the sources and drains of the memory transistors,
forming the first low doped region of the sources and drains of the logic transistors.
arranging spacers on the lateral edges of the gates of those logic transistors, and
forming the second highly doped region of the sources and drains of the logic transistors.